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[VHDL-FPGA-Verilog] VHDL_electronic_organ

Description: 简易电子琴，可以弹奏音乐。本课程设计主要内容是基于VHDL语言并利用数控分频器设计硬件电子琴，利用GW48作为课程开发硬件平台，键1至键8设计为电子琴键。某一个LED显示当前的按键的音节数。-Simple organ, can play music. The main contents of this curriculum design is based on the VHDL language and the use of digital hardware design divider organ, the use of curriculum development as GW48 hardware platform, key 1 to key electronic keyboard designed for 8. A button LED shows the current number of syllables.
Platform: | Size: 267264 | Author: lsb | Hits:

[VHDL-FPGA-Verilog] addDisplay

Description: 四人抢答器，用quartus编译过的，vhdl语言，说明详细，欢迎各位下载，-add display led
Platform: | Size: 330752 | Author: 吴小平 | Hits:

[SCM] LEDpingsheji

Description: LED显示屏控制系统及驱动程序的研究与设计(优秀硕士毕业论文)-LED display driver control systems and research and design (excellent Master Thesis)
Platform: | Size: 1710080 | Author: wang | Hits:

[VHDL-FPGA-Verilog] clock

Description: VHDL数字闹钟实现，运用八位LED显示-VHDL realization of the digital alarm clock, the use of eight LED display
Platform: | Size: 2048 | Author: 公孙齐桓 | Hits:

[VHDL-FPGA-Verilog] 01.ISE8.2

Description: 这个是我用的合众达试验箱里面的资料。合众达试验箱里面集成的是xilinx的virtex4，这个是在ise环境中审计的程序，包括led,da/ad转换实验，键盘实验，以及rtc读取和lcd显示等。-vhdl programs that used by xilinx virtex4
Platform: | Size: 14129152 | Author: 肖姗姗 | Hits:

[VHDL-FPGA-Verilog] DE2

Description: 使用 DE2板制作的多功能数字钟，含有选择功能，秒表，电子表，闹钟，用7-segment LED液晶显示，可以通过LCD看当时状态 附有仿真波形--Clk_Div,- Mode_Select,-Watch,-stop_watch,-Lcd_Module,-Total_Out source code，Simulation waveform
Platform: | Size: 3694592 | Author: 赵香君 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 74ls164 8位移位寄存器 串入并出-74ls164 8-bit shift register and a string into
Platform: | Size: 1024 | Author: fankexing | Hits:

[VHDL-FPGA-Verilog] rafal2

Description: VHDL project for FPGA SPartan 3 using IseWebpack 10.1. This is an implemetation of FSM for testing 7 segment with dot point 4 digit LED display.
Platform: | Size: 941056 | Author: nukom | Hits:

[SCM] S3_SW

Description: 这个程序是用来测试拨码开关与按键开关的， 当按下按键开关时，相应的led会点亮， 同理打开拨码开关相应的led也会点亮-This procedure is used to test switch DIP switch and button, when pressing the button switch, the corresponding led will light up, open the same token the corresponding DIP switch led will be lit
Platform: | Size: 188416 | Author: 刘飞 | Hits:

[VHDL-FPGA-Verilog] liushuideng

Description: 流水灯程序，１．在ＣＨ－３实验平台上通过ＬＥＤ０～ＬＥＤ７八位ＬＥＤ发光二极管实现流水灯显示，流水效果为LED灯依次亮起，第二个灯亮时第一个熄灭２．用按键切换产生２种流水效果-Process water lights, 1. CH-3 in the experimental platform LED0 ~ LED7 through eight light-emitting diode LED lights show the achievement of water, running water followed by the effect of LED lights turn on, and the second when the lights go out the first 2. Key switch with two kinds of water have the effect of
Platform: | Size: 1768448 | Author: 赵剑平 | Hits:

[Embeded-SCM Develop] deCPLDVHDLshijong

Description: 基于CPLD的VHDL语言数字钟（含秒表）设计 利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试方便、故障率低、修改升级容易等特点。 本设计采用自顶向下、混合输入方式（原理图输入—顶层文件连接和VHDL语言输入—各模块程序设计）实现数字钟的设计、下载和调试。 -CPLD based on the VHDL language digital clock (with stopwatch) design using a chip can be completed in addition to the clock source, buttons, speakers and display (LED) in addition to all functions of digital circuits. All digital logic functions are used in the CPLD device VHDL language. This design has a small and short design cycle (design process to achieve timing simulation), to facilitate debugging, fault rate is low and easy to modify the characteristics of the upgrade. The design uses a top-down, mixed input (input schematic- top-level file access and VHDL language input- the module program design) Design of digital clock, download and debug.
Platform: | Size: 95232 | Author: wuhuisong | Hits:

[VHDL-FPGA-Verilog] 48led

Description: 此软件用的是QuartusII 5.1的环境编写的CPLD内的程序，CPLD用的是EPM7128，实现的功能是对计算机的ISA总线读写操作，计算机通过ISA总线，再通过CPLD，来控制LED的亮和灭-This software is used in the preparation of QuartusII 5.1 environment within the CPLD procedures, CPLD using EPM7128, the function of the realization of the ISA bus on the computer to read and write operation, the computer through the ISA bus, and then through the CPLD, to control the LED' s Liang and poverty
Platform: | Size: 201728 | Author: hujianhua | Hits:

[VHDL-FPGA-Verilog] LED

Description: 这是一个用VHDL编写的LED显示程序，该程序虽然简单，但对一个初学的人来说也未必用不到，所以上传，希望能有人用到-This is a VHDL prepared with LED display program, the program is simple, but for a beginner who may not be less than, so upload the hope was to use
Platform: | Size: 1024 | Author: wangkai | Hits:

[VHDL-FPGA-Verilog] VHDLjianpan

Description: 一个VHDL键盘的设计，有去抖，能稳定在LED上显示。程序都已变好，你可以借鉴一下。-VHDL design of a keyboard, and to tremble, to stability in the LED display. Procedures have been changed for the better, you can learn from you.
Platform: | Size: 987136 | Author: ywb | Hits:

[VHDL-FPGA-Verilog] traffic

Description: 一个很好的交通灯控制的Verilog HDL实现方式，包括LED显示部分。-A good control of traffic lights to achieve the Verilog HDL, including the LED display.
Platform: | Size: 1024 | Author: keke | Hits:

[VHDL-FPGA-Verilog] LED_vhdl

Description: LED控制VHDL程序与仿真,FPGA驱动LED静态显示-led vhdl driver
Platform: | Size: 6144 | Author: jz | Hits:

[VHDL-FPGA-Verilog] LEDVHDL

Description: 8.2 LED控制VHDL程序与仿真 本节分别介绍采用FPGA对LED进行静态和动态显示的数字时钟控制程序。 1. 例1：FPGA驱动LED静态显示 --文件名：decoder.vhd。 --功能：译码输出模块，LED为共阳接法。 --最后修改日期：2004.3.24。 -8.2 LED control and simulation of VHDL procedures introduced in this section of the LED using FPGA static and dynamic display of digital clock control procedures. 1. Cases 1: FPGA-driven static LED display- File name: decoder.vhd.- Function: Decoding output module, LED connection for a total of Yang.- Last modified date: 2004.3.24.
Platform: | Size: 5120 | Author: wangnan | Hits:

[VHDL-FPGA-Verilog] key_4x4

Description: 4x4键盘结合LED动态显示，里面包含了键盘扫描、2进制转10进制BCD码、LED编码和LED动态显示-4x4 keyboard combination LED dynamic display, which contains the keyboard scan, 2 to 10 hexadecimal BCD hex code, LED codes and LED dynamic display
Platform: | Size: 134144 | Author: hao | Hits:

[Other] get_6675_temp_2

Description: MAXII 240 CPLD和6675 开发的0-1023.75度的温度传感数据采集系统，用seg7 LED显示，精度0.25度。探头是K型测温线，Quartus II 6.0调是通过，在cpld开发板上面试验成功-MAXII 240cpld and 0-1023.75 development of 6675 degrees C temperature sensor data acquisition system, using seg7 LED shows that the accuracy of 0.25 degrees. K-type temperature probe is a line, Quartus II 6.0 transfer is approved, the development board cpld successfully tested above. The MAX6675 performs cold-junction compensation and digitizes the signal from a type-K thermocouple. The data is output in a 12-bit resolution, SPI™-compatible, read-only format. This converter resolves temperatures to 0.25°C, allows readings as high as+1024°C, and exhibits thermocouple accuracy of 8LSBs for temperatures ranging from 0°C to+700°C. controller is cpld
Platform: | Size: 464896 | Author: 谭建平 | Hits:

[VHDL-FPGA-Verilog] daima

Description: 用VHDL语言设计一个8位加法器： 在八位加法器代码一中：加法器是由两个4位二进制加法器U1和U2组成的8位加法器逻辑电路，其中U1用来装载8位加法器中两个加数的低4位，而U2则用来装载高4位。在设计4位加法器时，定义输入信号量CIN、A、B以及输出信号量S、Cout。定义信号量SINT/AA/BB，将加数A和0并置后赋给AA，加数B和0并置后赋给BB，形成5位二进制数，这是为在做加法时发生溢出所做的处理，然后将加数AA与BB以及进位Cin相加赋给SINT，并将SINT的低4位赋给加数和S输出，同时将SINT最高位传送给Cout输出。在设计8位加法器时，定义一个信号量CARRY，将4位加法器U1的COUT赋给CARRY，再将CARRY的值赋给4位加法器U2的进位位Cin，8位加法器的高4位和低4位分别来自于4位加法器U2和U1。 而在八位加法器代码二中：8位加法器的设计不使用底层文件，直接设计为8位与8位的相加，该种方法在设计上更为简洁。在实验硬件连接上，可以使用LED七段数码管显示所得结果，使结果显示更为清晰明了。 -With VHDL language design 8 accumulators: in eight accumulator codes in one: The accumulator is 8 accumulator logic circuit which is composed of two 4 binary system accumulator U1 and U2, U1 uses for to load in 8 accumulators two addend low 4, but U2 uses for to load high 4. When designs 4 accumulators, the definition input signal measures CIN, A, B as well as the output signal measures S, Cout. The definition signal measures SINT/AA/BB, after addend A and 0 juxtapositions, bestows on for AA, after addend B and 0 juxtapositions, bestows on for BB, forms 5 binary system number, this is for when does the addition has processing which the overflow does, then as well as carries Cin addend AA and BB to levy additional taxes for SINT, and the SINT low 4 taxes for the addend and the S output, simultaneously transmits the SINT highest order to the Cout output. When designs 8 accumulators, defines a signal to measure CARRY, bestows on 4 accumulator U1 COUT for CARRY, bestows on again the CARRY
Platform: | Size: 9216 | Author: SAM | Hits:
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